(1) Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and, more particularly, to a nonvolatile semiconductor memory device such as an electrically erasable programmable ROM (hereinafter referred to as "EEPROM") in which the data stored in a memory transistor can be erasable and a new data can be written therein.
(2) Description of the Related Art
Several kinds of non-volatile semiconductor memory devices in which the stored data does not disappear even when a power supply is turned off have been conventionally researched and developed. In recent years, development of EEPROM among them has been advanced speedily so that several kinds of products thereof have been in practical use. There are EEPROMs having a wide variety of structures. Recently, the EEPROM with memory transistors connected in series has been proposed (R. Shirota et al. "Technical digest of 1988 symposium on VLSI technology", pp. 33-34).
Now referring to FIG. 1 showing an equivalent circuit of one example of the those conventional non-volatile semiconductor memory devices, the circuit arrangement of the related art will be explained below.
In FIG. 1, reference symbols Q.sub.Si.j (i=1.about.2 and j=1.about.4) denote selecting transistors and reference symbols Q.sub.Mi.j (i=1.about.2, j=1.about.6) denote memory transistors. The control electrodes of the memory transistors Q.sub.Mi.j (i=1.about.2, j=1.about.6) are connected with word lines Xi (i=1.about.6) for each row. Among the selecting transistors Q.sub.Si.j (i=1.about.2, j=1.about.4), the gate electrodes of first selecting transistors (Q.sub.S1.1, Q.sub.S1.3 ; Q.sub.S2.1, Q.sub.S2.3) connected with bit lines Y1 and Y2 are, respectively, connected with the corresponding first select lines Z1 and Z3 and, in the same manner, the gate electrodes of second of selecting transistors (Q.sub.S1.2, Q.sub.S1.4 ; Q.sub.S2.2, Q.sub.S2.4) connected with a source line S are connected with the corresponding second select lines Z2 and Z4, respectively.
Two groups of transistors each group comprising one first selecting transistor, three memory transistors and one second selecting transistor are connected in series between the bit line Y1 and the source line S and between the bit line Y2 and the source line S, respectively. The bit lines Y1 and Y2 are connected to the drain electrodes of the first selecting transistors (Q.sub.S1.1, Q.sub.S1.3 ; Q.sub.S2.1, Q.sub.S2.3) for each column.
FIG. 2A is a plan view of a group of transistors arranged between the bit line and the source line of the memory device, and FIG. 2B is a sectional view taken along the line A--A' in FIG. 2A. In FIGS. 2A and 2B, the numeral 21 denotes a semiconductor substrate; 22a denotes a drain region of the first selecting transistor; 22b denotes a source region of the second selecting transistor; 22c denotes impurity diffusion regions connecting the respective selecting and the memory transistors in series; 23a, 23b denote gate insulating films of the first and second selecting transistors; 24 denotes a first gate insulating film of the memory transistor; 25 denotes a second gate insulating film of the memory transistor; 26 denotes a floating gate; 27 denotes a control (regular) gate; 28a, 28b denote gate electrodes of the first and second selecting transistors; 29 denotes an inter-layer insulating film; 30 denotes a contact hole; and 31 denotes a metal wiring for the bit line.
The structural feature of the above non-volatile semiconductor memory device resides in that the first gate insulating film 24 of the memory transistor is as thin as 90 .ANG., so that tunneling action is likely to occur between the floating gate electrode 26 and the semiconductor substrate 21 and also between the floating gate electrode 26 and a source/drain electrode. Therefore, using the operating theory based on such a phenomenon, this non-volatile semiconductor memory device electrically writes and erases data in the memory transistor.
The operating theory of the above non-volatile semiconductor memory device will be explained with the attention being paid to the group of transistors (Q.sub.S1.1, Q.sub.M1.1, Q.sub.M1.2, Q.sub.M1.3, Q.sub.S1.2) connected in series (FIG. 1) assuming that these transistors are all of N-channel type. TABLET 1 shows the respective potentials at the bit line Y1, the first and second select lines Z1 and Z2, and the word lines X1, X2 and X3 in each mode of data erasing, data writing and data reading. The values in the table are expressed in volt (V).
TABLE 1 __________________________________________________________________________ OPERATION MODE ERASURE WRITE READ SELECTED NO TRANSISTOR SELECTIVITY QM1.1 QM1.2 QM1.3 QM1.1 QM1.2 QM1.3 __________________________________________________________________________ BIT LINE 0 20 20 20 1 1 1 Y1 FIRST 5 20 20 20 5 5 5 SELECT LINE Z1 WORD LINE 17 0 20 20 0 5 5 X1 WORD LINE 17 0 0 20 5 0 5 X2 WORD LINE 17 0 0 0 5 5 0 X3 SECOND 5 0 0 0 5 5 5 SELECT LINE Z2 SOURCE LINE 0 0 0 0 0 0 0 __________________________________________________________________________
It should be noted that "data erasure" means to inject electrons into the floating gate electrode and "data write" means to extract the electrons from the floating gate electrode.
First, an explanation will be given of the mode of erasing data stored in the transistors Q.sub.M1.1, Q.sub.M1.2 and Q.sub.M1.3. The bit line Y1 and the source line S are set at a ground potential (=0 V) and the word lines X1, X2 and X3 are set at a high positive voltage, e.g., 17 V. The first and the second select lines Z1 and Z2 are set at 5 V, so that the channel potential and the potentials at the source and drain electrodes of each of the memory transistors Q.sub.M1.1, Q.sub.M1.2 and Q.sub.M1.3 are fixed to 0 V. Then, the positive high voltage applied to the control gate electrode 27 of each of the memory transistors Q.sub.M1.1, Q.sub.M1.2 and Q.sub.M1.3 strengthens the electric field in the first gate insulating film 24, so that Fowler-Nordheim electron tunneling phenomenon (hereinafter referred to as "F-N tunneling phenomenon") takes place. This injects electrons from the semiconductor substrate 21 and the impurity diffusion layer 22c into the floating gate electrode 26 through the first gate insulating film 24. Thus, the threshold voltage of each of the memory transistors Q.sub.M1.1, Q.sub.M1.2 and Q.sub.M1.3 is boosted. The resultant state is the state where the data have been erased. This data erasing mode has no selectivity of the memory transistors so that the data stored in all the memory transistors are simultaneously erased.
Next, an explanation will be given on the mode of writing or storing data in the memory transistor Q.sub.M1.1, Q.sub.M1.2 or Q.sub.M1.3. A high positive voltage, e.g., 20 V is set to the bit line Y1, the first select line Z1, and the word line(s) X1, X2 and X3 for the memory transistor(s) nearer to the bit line Y1 than the memory transistor Q.sub.M1.1, Q.sub.M1.2 or Q.sub.M1.3 in which data are to be stored. Also, at the same time, a ground potential is set to the source line S and the word line(s) X1, X2 and X3 for the memory transistor itself to be stored with data and for the memory transistor(s) nearer to the source line S than the memory transistor Q.sub.M1.1, Q.sub.M1.2 or Q.sub.M1.3 in which data are to be stored. Then, the control gate electrode 27 of the memory transistor to be stored with data is at the ground potential and the drain electrode thereof is at the high positive potential of 20 V, so that a strong electric field is applied to the first gate insulating film 24 of the memory transistor to be stored with data. Thus, the electrons are emitted from the floating gate electrode 26 of the memory transistor to be stored with data, towards the impurity diffusion layer 22c based on the F-N tunneling phenomenon. At this time, the memory transistor in which the high voltage has been applied to its control electrode 27 and its drain electrode serves as only a transfer gate, and since the electric field applied to the first gate insulating film 24 of the memory transistor concerned in a biased state is weak, the F-N tunneling phenomenon does not occur thereat.
Further, in the memory transistor(s) positioned nearer to the source line S than the memory transistor to be stored with data, its control gate electrode 27 is at the ground potential but the potential at its drain electrode does not go up because it is cut off by the memory transistor to be stored with data. As a result, the strength of electric filed in the first gate insulating film 24 becomes weak and so the F-N tunneling phenomenon does not occur. Thus, the selective writing of data in the memory transistor can be attained. If the number of memory transistors to be stored with data is plural, data are successively stored in the plural memory transistors connected with the selecting transistor Q.sub.S1.1 in the order of the memory transistors nearer to the source line S in the way as described above. This intends to protect the data already stored in the memory transistor from the electric field stress during the data writing in the memory transistor and to prevent the variations in the threshold voltage of the memory transistor. Additionally, the second select line Z2 connected with the gate electrode of the second selecting transistor Q.sub. S1.2 must be kept at 0 V during the data writing. This is because, in the case where the memory transistor already stores data and the channel current flows therethrough even when the potential at the control gate electrode thereof is 0 V, such channel current must be cut off.
Lastly, an explanation will be given on the mode of reading out of the data in the memory transistors.
In this mode, the bit line Y1 is fixed to 1 V, and the first and second select lines Z1 and Z2 are fixed to 5 V. Further, only the word line X1, X2 or X3 which is connected with the memory transistor from which the data are to be read out is set at the ground potential and all the other remaining word lines are set at 5 V. In this state, if the selected memory transistor is in an erased state, its threshold voltage is a positive value so that no current flows from the bit line Y1 to the source line S. On the other hand, if the selected memory transistor is in a written state, the threshold voltage thereof is a negative value so that there flows a current from the bit line Y1 to the source line S. All the other remaining non-selected memory transistors serve as transfer gates. It should be noted that in this operation mode, the threshold voltage of each of the memory transistors must be kept controlled lower than the control gate voltage, e.g., 5 V.
An explanation will be given on the bias conditions of the four transistors in a write state with the memory transistors Q.sub.M1.3, Q.sub.M2.3, Q.sub.M1.6 and Q.sub.M2.6 being taken as representatives amongst the four transistor groups each comprising the transistors connected in series as shown in FIG. 1. TABLE 2 shows the potentials at each of the bit lines, each of the word lines and the first and second select lines.
TABLE 2 __________________________________________________________________________ FIRST SECOND FRIST SECOND WRITE BIT LINE BIT LINE SELECT SELECT SELECT SELECT WORD LINE WORD LINE TRANSISTOR Y1 Y2 LINE Z1 LINE Z2 LINE Z3 LINE Z4 X3 X6 __________________________________________________________________________ QM1.3 20 10 20 0 0 0 0 0 QM2.3 10 20 20 0 0 0 0 0 QM1.6 20 10 0 0 20 0 0 0 QM2.6 10 20 0 0 20 0 0 0 __________________________________________________________________________
The respective control gate electrodes 27 of the memory transistors Q.sub.M1.3, Q.sub.M2.3 are connected with the same word line X3, and those of the memory transistors Q.sub.M1.6 and Q.sub.M2.6 are connected with the same word line X6. Therefore, selective write for the memory transistors Q.sub.M1.3, Q.sub.M2.3 and the memory transistors Q.sub.M1.6 and Q.sub.M2.6 is executed by controlling the potentials at the bit lines Y1 and Y2.
Now, assuming that data will be stored in Q.sub.M1.3 but data will not be stored in Q.sub.M2.3. Then, Q.sub.M1.3 is placed in a write bias state as described above but, since the data should not be stored in Q.sub.M2.3, the bit line Y2 is held at an intermediate voltage of 10 V. Thus, the transistor Q.sub.M2.3 is biased in such a state where 0 V is applied to its control gate electrode and 10 V is applied to its drain electrode. While the transistor Q.sub.M1.3 is biased in such a state where 0 V is applied to its control gate electrode and 20 V is applied to its drain electrode, the drain electrode of the transistor Q.sub.M2.3 has a low voltage of 10 V, so that the electric field applied to the first gate insulating film is lower in the Q.sub.M2.3 than in the Q.sub.M1.3. Therefore, the F-N electron tunneling phenomenon will not occur in the Q.sub.M2.3 so that the data is not erroneously stored in this transistor Q.sub.M2.3. In this state, the memory transistors Q.sub.M2.1 and Q.sub.M2.2 are biased in such a state that 20 V is applied to their control gate electrodes and 10 V is applied to their drain electrodes. In this state also, the potential difference between the control gate electrode and the drain electrode is smaller than that in the erasing mode, so that the F-N electron tunneling phenomenon does not occur. Therefore, during the writing operation, the data stored in the non-selected memory transistors connected with the non-write bit line (Y2) are not erased. With respect to the transistors Q.sub.M1.6 and Q.sub.M2.6, the word line X6 is biased to 0 V, and their drain electrodes are separated from the bit lines Y1 and Y2 by the first selecting transistors Q.sub.S1.3 and Q.sub.S2.3 with their gate electrodes fixed to 0 V by the first select line Z3. Therefore, no electric field stress is applied to the memory transistors, so that no erroneous erasure and write occur in these memory transistors.
As described above, it is apparent that in order to obviate erroneous write for the memory transistors connected with a common word line, the intermediate potential of, e.g., 10 V is required. Also, in the case where the bit line is controlled using only two values of, e.g., 0 V and 20 V but without using the intermediate potential (10 V), the erroneous write for the memory transistors connected with the common word line can be avoided during the write operation. But, erroneous erasure for the non-selected memory transistors connected with the non-write bit line necessarily advances, so that their threshold voltage will be increased unintentionally. Such a phenomenon is conspicuous in the memory transistors nearer to the bit line and also problematic because the number of times of erasure during the write increases with the number of the memory transistors connected in series. This problem, if the threshold voltage of the non-write transistor exceeds the voltage applied to the control gate electrode during the read operation, leads to a fatal result of erroneous data read.
As understood from the above description, the non-volatile memory device constructed so as to include memory transistors connected in series has the following features.
(1) The Fowler-Nordheim (F-N) electron tunneling phenomenon is used in both the erasing and writing of the data;
(2) In addition to the memory transistors, two selecting transistors are connected in series between the bit line and the source line; and
(3) In order to avoid unintentional data erasure in the non-selected transistor during the data writing, three biasing potentials (high, intermediate and low) are used for the bit line.
The conventional non-volatile memory device described above, however, has the following defects.
Three levels of biasing potentials for the bit line are required for the selective write and also the F-N tunneling phenomenon must be controlled using the potential difference between the intermediate potential and the low potential, so that these potentials are required to be set in a relatively narrow range. Particularly, if the intermediate potential is lower or higher than a prescribed value, it gives rise to malfunction, so that an appropriate controlling of the same is a difficult matter in the conventional device.
Further, there is the theoretical problem of excessive erasure, that is, the threshold voltage of a memory transistor exceeds the control gate voltage during a read operation. In order to solve this problem, an erasing voltage must be precisely set and controlled, and the method of fabricating memory transistors is also limited. This lowers the production yield of the memory device.
Moreover, since both the write and erasure modes use the F-N tunneling phenomenon, they require a relatively high voltage. Therefore, both the transistors for bit line controlling and word line controlling must be transistors having high breakdown voltage characteristics. Further, since only the F-N tunneling phenomenon can be utilized for the writing and erasing modes, the first gate insulating film of the memory transistor concerned is required to be a thin silicon oxide film of, e.g., 100 .ANG. or less. It is difficult to control the thickness and the quality of the gate insulating film, so that the production yield of the memory device will be lowered.
The conventional non-volatile semiconductor memory device has also a defect that the operation of writing data in the memory transistors can be made only serially or sequentially from the transistor positioned at the side of the source line. Therefore, in the write operation, it is necessary that, after all bits of data are necessarily once erased, re-programming be executed. For this reason, the functions of word-erasing and word-writing cannot be achieved by the conventional memory device, so that it takes a long time to make the re-programming. As a result, its use as a large capacity non-volatile memory will be extremely limited.